Recently, with rapid distribution of information via media such as computers, semiconductor devices have rapidly progressed. In the functional aspect, semiconductor devices are required to be operated at high speeds and, at the same time, to have mass storage capability. In response to these functional requirements, semiconductor manufacturing technology has made progress toward enhancing integration, reliability, response speed, and so on. As primary technology for enhancing integration of the semiconductor devices, fine processing technology becomes more and more strict in its requirements.
One of technologies for enhancing such integration is planarization on technology. In recent semiconductor manufacture, chemical mechanical polishing (CMP) of directly polishing an object to be polished using a polishing pad is mainly used.
The CMP is disclosed in U.S. Pat. No. 5,896,870 (International Business Machines Corporation) and U.S. Pat. No. 5,922,620 (Kabushiki Kaisha Toshiba). However, in the CMP, an object to be polished is polished with the use of a polishing pad while polishing particulates called slurry are injected, so that it is easy for a scratch, etc. to be generated on the polished object after polishing. This scratch is responsible for generation of a metal residue during a subsequent process such as a process for forming a metal layer pattern.
Further, a metal residue, a portion to be polished, which is not still polished and left after the CMP is performed, is easily generated. This metal residue is generated from non-uniform planarization during the CMP as a wafer is scaled up to large diameter and a height difference between surfaces of processed layers is increased.
Particularly, in the case where the metal residue is generated during formation of the metal layer pattern by means of the CMP, this metal residue causes a bridge, etc. to be generated between the metal layer patterns, so that a failure occurs at the semiconductor device.
FIGS. 1 to 5 are process sectional views for explaining a known method of manufacturing a semiconductor device.
FIG. 1 shows a process for forming an insulating layer 103 on a semiconductor substrate 101 on which a substructure 102 is formed. To be specific, the substructure 102, such as a gate electrode, a polysilicon line, or so forth, which constitutes the semiconductor device, is formed on the semiconductor substrate 101. The insulating layer 103 is formed of a dielectric, such as silicon oxide, boro-phospho-silicate glass (BPSG), or so forth, on the semiconductor substrate 101 on which the substructure 102 is formed by chemical vapor deposition (CVD).
FIG. 2 shows a process for planarizing the insulating layer 103. The insulating layer 103 is polished and planarized by the CMP. Here, a scratch 104a and so-called a dishing 104b (i.e., where a space between patterns is hollowed) are generated on the planarized insulating layer 103. The scratch 104a and the dishing 104b result in generation of the metal residue while a following metal layer pattern is formed.
FIG. 3 shows a process for forming an opening 105 at the planarized insulating layer 103. The opening 105 is formed by forming a photoresist pattern (not shown) for exposing a part of the top surface of the semiconductor substrate 101 and a part of the top surface of the substructure 102 on the planarized insulating layer 103, etching the planarized insulating layer 103 using the photo resist pattern as an etch mask, and exposing the part of the top surface of the semiconductor substrate 101 and a part of the top surface of the substructure 102.
FIG. 4 shows a process for forming a metal layer 106 on the insulating layer 103. Specifically, the metal layer 106 is formed by depositing a metal material, such as aluminum (Al), tungsten (W), molybdenum (Mo) or the like, on the insulating layer 103 by means of sputtering to fill the opening 105.
FIG. 5 shows a process for polishing the metal layer 106 until the top surface of the insulating layer 103 is exposed and removing the metal layer which exists except the opening.
According to the above-mentioned method, as shown, the metal material is buried in the scratch 104a and the dishing 104b generated during polishing of the insulating layer 103. The metal material, which is buried in the scratch 104a and the dishing 104b after the metal layer 106 is polished, is formed as a metal residue remaining on the top surface of the insulating layer 103. Further, a part of the metal material, which is left without being polished after the metal layer 106 is polished, is also formed as such a metal residue on the top surface of the insulating layer 103. The metal residue leads to a failure of the semiconductor such as a metal bridge during formation of the metal layer pattern having a fine design rule.